VHDL Architecture Declaration Reference Form
Use this form to document and reference the details of a VHDL architecture declaration. Please provide clear and concise information for each section.
Entity Name
*
Architecture Name
*
Brief Description
*
Library/Package Usage
Generics (if any)
Ports Overview
*
Signals/Variables Used
Process/Block Summary
Reference Links (optional)
Additional Notes
Submit Reference
Should be Empty: