FIFO Buffer Sizing Questionnaire Form
Provide key design details to determine optimal FIFO buffer sizing for your application.
Application Type
*
Please Select
Data Transfer
Video/Imaging
Audio/Signal Processing
Networking/Packet Buffer
General Purpose
Other
Data Width (bits)
*
Required Buffer Depth (entries)
*
Are the read and write clock domains the same?
*
Yes, single clock domain
No, asynchronous (dual clock domains)
Peak Data Throughput (Mbps)
*
Typical Burst Size (words)
*
Maximum Acceptable Latency (cycles)
Reset Behavior
*
Synchronous Reset
Asynchronous Reset
No Reset Required
Implementation Technology
*
Please Select
FPGA
ASIC
SoC
Other
Special Requirements or Notes
Submit
Should be Empty: